A digital signal computer, or digital signal processor (DSP), is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing and speech recognition. Digital signal processor applications are typically characterized by real time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Thus, designs of digital signal processors may be quite different from those of general purpose computers.
One approach that has been used in the architecture of digital signal processors to achieve high speed numeric computation is the Harvard architecture, which utilizes separate, independent program and data memories so that the two memories may be accessed simultaneously. This architecture permits an instruction and an operand to be fetched from memory in a single clock cycle. Frequently, the program occupies less memory space than the operands for the program. To achieve full memory utilization, a modified Harvard architecture utilizes the program memory for storing both instructions and operands. Typically, the program and data memories are interconnected with the core processor by separate program and data buses.
When both instructions and data (operands) are stored in the program memory, conflicts may arise in the fetching of instructions. Certain instruction types may require data fetches from the program memory. In the pipelined architecture which may be used in a digital signal processor, the data fetch required by an instruction of this type may conflict with a subsequent instruction fetch. Such conflicts have been overcome in prior art digital signal processors by providing an instruction cache. Instructions that conflict with data fetches are stored in the instruction cache and are fetched from the instruction cache on subsequent occurrences of the instruction during program execution. In general, the instruction cache is a satisfactory solution to conflicts for memory access. However, under certain circumstances problems may arise. For example, when a routine being executed repetitively does not fit in the instruction cache, that routine is executed relatively slowly, and performance is degraded. In addition, cache misses, which occur when the required instruction is not located in the instruction cache, reduce the speed of program execution.
Although the modified Harvard architecture used in conjunction with an instruction cache provides excellent performance, the need exists for further enhancements to the performance of digital signal processors. In particular, the marketplace requires increased computation rates and enhanced computation performance.
As described in Byte, November 1994, pages 114-116, the PowerPC 620 microprocessor utilizes a data cache having a 128 bit data bus. The data cache has the disadvantage that cache misses reduce the speed of program execution. In the PowerPC 620, up to four instructions are dispatched per cycle to the execution units.